In the mid 1960's, it was observed by semiconductor manufacturers that the number of transistors fabricated on integrated circuits (“chips”) was doubling about every 18 months. This trend has continued and is now termed “Moore's Law.” The number of transistors is viewed as a rough measure of computer processing power, which, in turn, corresponds to data processing speed. Another version of Moore's Law relates to memory capacity or the density of memory cells in memory chips. Although Moore's Law was originally made as an observation, over time Moore's Law has became widely accepted by the semiconductor industry as a goal for increasing computer processing power and memory capacity. As a result, semiconductor manufacturers have developed technologies for reducing the size of chip components to microscale and even nanoscale dimensions. These chips are typically embedded in packages, and the packages may be connected to other chips or electronic devices by way of signal wires patterned on a circuit board.
FIGS. 1A-1C illustrate an example chip and package with circuit board interconnects for transmitting data to other chips and devices. FIG. 1A illustrates a top view of an example chip 102 and package 104. The package 104 is connected to four separate sets of nine parallel signal wires 106-109, each set of signal wires is called a “wire bus.” Each wire bus 106-109 transmits data in parallel between the chip 102 and other chips or devices (not shown) that may be located on the same circuit board or different circuit boards. For example, the wire bus 106 may be connected directly to a random access memory (“RAM”) chip, which is located on the same circuit board (not shown), and the wire bus 108 may be connected to a sensor, which is located on a different circuit board (not shown).
FIG. 1B illustrates an enlargement of the chip 102 and the package 104 shown in FIG. 1A. The chip 102 includes a number of contact pads located near the perimeter of the chip 102, such as contact pad 110, and the package 104 includes a number of pins which are located around the perimeter of the package 104, such as pin 112. Each contact pad is connected to a single pin via a lead wire, and each pin is connected directly to a wire in a wire bus. For example, the contact pad 110 is connected to the pin 112 via a lead wire 114, and the pin 112 is connected to a bus wire 116. Each electrical signal transmitted or received by the chip 102 is carried by a contact pad, a lead wire, a pin, and one of the wires in a wire bus.
FIG. 1C illustrates a cross-sectional view of the chip 102 and the package 104 shown in FIG. 1B. As shown in FIG. 1C, the chip 102 and the package 104 are supported by a circuit board 118. The chip 102 comprises a Si transistor layer 120, a local interconnect 122, and a global interconnect 124. The Si transistor layer 120 comprises transistor components, electrical current sources, and drains (not shown). Vias in the local interconnect 122, such as via 126, interconnect devices in the Si transistor layer 120, and vias in the global interconnect 124 interconnect the Si transistor layer 120 to the contact pads. For example, via 128 interconnects the Si transistor layer 120 to the contact pad 110. The local interconnect 122 serves as a multiplexer by distributing signals between components of the Si transistor layer 120, and the global interconnect 124 serves a multiplexer by distributing signals generated within the Si transistor layer 120 to other chips or devices. For example, via 128 transmits signals to the contact pad 110, which is coupled to the wire 116 by way of the pin 112 and the lead wire 114.
In order for a first chip to transmit data to a second chip, the first chip multiplexes one or more signals encoding the data. The signals are multiplexed by the global interconnect around the perimeter of the first chip and transmitted to the second chip over the wire bus. Each wire in a wire bus carries one of the multiplexed signals. The global interconnect of the second chip demultiplexes the signals in order to obtain one or more signals that the second chip uses to process the data. FIG. 1D illustrates a wire bus interconnect between an example microprocessing (“CPU”) chip 130 and an example RAM chip 132. A wire bus connecting the CPU chip 130 to the RAM chip 132 comprises 5 bus wires 134-138. Suppose the CPU chip 130 generates data to be stored temporarily in the RAM chip 132. The CPU chip 130 multiplexes the signal corresponding to the data by distributing the signal over contact pads 140. The distributed signal can then be transmitted over the bus wires 134-138 to the contact pads 142 of the RAM chip 132. The RAM chip demultiplexes the distributed signals received by contact pads 142 into fewer signals that can be used to store the data in one or more memory cells of the RAM chip 132.
Although recent semiconductor fabrication methods have made it possible to increase the density of transistors and memory cells in chips, the number of wires needed to interconnect these chips has increased, which has increased the need for larger circuit board surface areas and longer bus wires. As a result, the time needed to transmit data between chips, measured in chip clock cycles, has increased. Although semiconductor manufacturers have responded by developing techniques for reducing the cross-sectional dimensions of the wires so that more wires can be fit into smaller surface areas, there exist limitations on these cross-sectional dimensions. For example, as wire sizes decrease and more wires are packed into a smaller surface area, the number of interference effects increase, such as interference between signals transmitted on adjacent wires, and the number of thermal effects increase, because wire resistance increases as the wire cross-sectional dimensions decrease. These physical limitations make it unlikely that semiconductor manufacturers can continue to take advantage of the miniaturization offered by microscale and nanoscale semiconductor fabrication techniques. Furthermore, the intrinsic capacitance of the multiplexing and demultiplexing carried out at chip boundaries can greatly exceed the capacitance of the chip, which reduces signal speed transmission between chips. Manufacturers, designers, and users of computing devices have recognized a need for interconnects that provide high bandwidth and high-speed global interconnects between chips and other electronic devices.